A binary-counter-based test generator in compact testing systems

The use of the modified binary counter, as a test generator, is shown to allow to detect 100% of errors of the certain type in the combination scheme in the corresponding choice of the signature analyzer. If, as a result of reswitching, it is possible to apply signals from S counter minor digits to arbitrary S inputs of the programmable logic matrix then all the errors of multiplicity S and less in the column of the unit AND of the programmable logic matrix will be detected as a result of testing

Detection of single and multiple errors using the optimal signature analyzer

The signature analyzers (SA) are widely applied in the systems of built-in testing of digital devices. At the present time, the analyzers designed on the basis of a shift register with linear feedbacks are mostly used. A study of the influence of an error model change on the SA quality is of interest. Assurance of the sequence control using the optimal SA is studied in the cases of single and multiple errors. Quality criteria are introduced that are used for estimation of the optimal SA in the frames of error models. Quality of the usual linear SA is evaluated by the introduced criteria

Realizations of optimal signature analyzer

The realizations of optimal nonlinear signature analyzer are proposed. The analyzer is tuned for the testing sequence. The analyzer optimizes the number of signature sequences. It appears that this analyzer is essentially more effective in comparison with linear one. One of the practical realizations contains binary counter which is complicated device. Linear shift register with feedback is proposed to use instead of binary counter. Proposed circuit for nonlinear signature analyzer enable to reduce the number of sequences with equal signatures

Detection of erroneous sequences by nonlinear signature analyzer

The notion of optimal signature analyzer for the testing of given binary sequence is introduced. The analyzer is designed via initial sequence and is nonlinear. The model of errors is such that initial sequence can be replaced by any other. Proposed nonlinear analyzer has essentially better performances in comparison with linear signature analyzer. The testing with the help of the analyzer has several peculiarities. Particularly, in some cases the length of testing sequence is decreased

Exhaustive testing and signature analysis

The possibility of error detection and exhaustive error testing during functioning off programed logic matrix are investigated. It is shown that the error can be missed under some relations between test generator and signature analyser matrices. The generator and analyser are linear sequential machines. Thus, the theory of linear sequential machines is used for the investigation. It appears that the use of test generator on the basis of linear sequential machine and signature analyser leads to the missing of many errors. Hence, the application of this pair is not efficient

A New Method for Slant Calculation in Off-Line Handwriting Analysis

© 2018 IEEE. In this paper, we propose a new method for estimating the slant of word in handwritten text. The method allows a researcher to analyze snippets of a picture containing a few words in different lines. The main goal of the research is to present a tool to observe small changes of slant in the text during work. Student check sheets were used as a database for the research. Some changes in slant depending on speed of writing are discovered

Tuning circuits in systems of built-in testing

Systems of built-in testing contain a test generator and a signature analyzer (SA). At last time expedience of the generator and SA selection for testing a given plant has been cleared up. Realization of this requirement assumes the modification possibility of a generator and a SA. Besides, in the case of multi-input SA efficiency of SA application over the fields (GF(2M) (m>1) has been proved. In this case circuits realizing the elements product in these fields are required. A regular tuning structure is suggested for calculation of the product of matrix into vector over the field GF(2). Possible its applications in tuning test generators and SA in systems of built-in testing are shown

Ternary jitter-based true random number generator

© Published under licence by IOP Publishing Ltd.In this paper a novel family of generators producing true uniform random numbers in ternary logic is presented. The generator consists of a number of identical ternary logic combinational units connected into a ring. All the units are provided to have a random delay time, and this time is supposed to be distributed in accordance with an exponential distribution. All delays are supposed to be independent events. The theory of the generator is based on Erlang equations. The generator can be used for test production in various systems. Features of multidimensional random vectors, produced by the generator, are discussed

Ternary jitter-based true random number generator

© Published under licence by IOP Publishing Ltd.In this paper a novel family of generators producing true uniform random numbers in ternary logic is presented. The generator consists of a number of identical ternary logic combinational units connected into a ring. All the units are provided to have a random delay time, and this time is supposed to be distributed in accordance with an exponential distribution. All delays are supposed to be independent events. The theory of the generator is based on Erlang equations. The generator can be used for test production in various systems. Features of multidimensional random vectors, produced by the generator, are discussed

Asynchronous Linear Combinational Circuits as a Base for Programmable Logic Device. Binary and Ternary Cases

© 2016Programmable logic devices on base of asynchronous combinational circuits with feedback are considered. The main aim of the research is to obtain a method for designing a circuit with a set of prescribed stable states or a circuit without stable states — a generator of true random numbers. Both the cases of binary and ternary logics are studied